DARPA Launches Automatic Implementation of Secure Silicon Program, Aims to Design Security into Microchips

DARPA has launched the Automatic Implementation of Secure Silicon (AISS) program – a four-year project seeking ways to design security features into microchips as they are being manufactured. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity.

“Today, it can take six to nine months to design a modern chip, and twice as long if you want to make that same design secure,” said Serge Leef, a program manager in DARPA’s Microsystems Technology Office (MTO). “While large merchant semiconductor companies are investing in in-house personnel to manually incorporate security into their high-volume silicon, mid-size chip companies, system houses, and start-ups with small design teams who create lower volume chips lack the resources and economic drivers to support the necessary investment in scalable security mechanisms, leaving a majority of today’s chips largely unprotected.”

The two AISS research teams are made up of:

  • Synopsys, Arm, Boeing, Florida Institute for Cybersecurity Research at the University of Florida, Texas A&M University, UltraSoC, and the University of California, San Diego; and,
  • Northrop Grumman, IBM, University of Arkansas, and University of Florida.

The AISS program will focus on two areas that can address four types of microchip vulnerability: “side channel attacks, hardware Trojans, reverse engineering, and supply chain attacks, such as counterfeiting, recycling, re-marking, cloning, and over-production.” The overall objective of the program is to develop a design tool and IP ecosystem – to include tool vendors, chip developers, IP licensers, and the open source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive.

“The ultimate goal of the AISS program is to accelerate the timeline from architecture to security-hardened RTL from one year, to one week – and to do so at a substantially reduced cost,” said Leef. “AISS will drive revolutionary advances in design productivity and have a dramatic and positive impact on our electronic supply chain security.”